Danny added a I2S output mod to my CD94, because I insisted on proper CD94->Dac cabling (not loose wires, I have kids who like to yank at wires). If signal strength is a concern, then Danny's mod is an option.
I don't think we can say the long wire run is out of the picture. The whole chain is in the mix (right back to choice of CD-R and burner). But there is probably bigger fish to fry than focussing any more time on optimising the I2S part of the chain.
WRT clock loading versus versus I2S cable driving, they are 2 separate things and not really directly interactive.
WRT your I2S cable drivers, in the scheme of things I don't know that it brings much to the party.
The I2S signal needs to be directly reclocked by the oscillator and as such ideally put on the clock board.
A zenclock would have maybe 10 to 100 x lower jitter than the I2S generating circuitry in CD94.
So in effect the re clocked I2S driver board may well be a bigger improvement than the clock itself.
There are other issues:
a) 5V logic level is not optimum for feeding I2S of TDA1541
b) There are many different types of logic for driving I2S, some noisier than others. Finding information on jitter
generated by various logic types is very difficult. I've built up a data base of info on this stuff but it took a lot of
research.
As you can see it's just not quite as simple as first appears.
OK that's enough information for one post - and enough time wasted. Too much to do atm.
Z