Regardless of the starting voltage, a single-ended clock, like the I2S clock, will degrade over distance. A good clock requires fast transitions because slow transitions lead to uncertainty in determining exactly when the clock changes logical polarity and that creates jitter. Not only is the I2S clock single-ended, it is not pre-conditioned and is rarely transmitted with a proper driver. Usually it’s just the output if a simple logic gate. That’s why my preference is to slave the digital source to the DAC clocks and not the other way around.
WRT slaving source off the DAC clock - yes this is a good solution.
In fact the DAC that Steven used before the series of 'Killer DAC's' was configured this way.
The master clock was inside DAC box, it was sent back to the transport with a dedicated BNC connected line.
So jitter was very low. However there are other issues and added complexity.
I think I2S is a good solution, most of the people here who are using it, have very short connection distances.
To put it in perspective, I think a badly implemented I2S, even with sub optimal driver is better than a receiver
chip and it's inferior PLL generated clock. And that would mirror the results most people have had when implementing I2S.
Also it is not that difficult, especially with some logic types today to do I2S extremely well.
